This invention generally relates to data communication, and more specifically to the efficient conversion between parallel and serial data communication, and conversion between serial and parallel data communication.
Data communication requiring conversion between serial and parallel data formats, and circuits performing that conversion, are used extensively in modern electronics. Conventional methods of conversion require that a circuit operate in two modes: a first mode in which the circuit receives data in serial bit form and outputs data in parallel bit form; and a second mode whereby the circuit receives data in parallel bit form and outputs data in serial bit form. While the first and second modes can operate concurrently, there is a time when the serial input of the first mode must be suspended to allow for the parallel input of the second mode.
Conventional conversion designs often employ a serial input/parallel output, parallel input/serial output N-bit register. The register receives mode and control input which regulates its operation. In operation, the register receives mode and control input to simultaneously load N data bits from the parallel inputs, then sequentially shift each of the data bits out via the serial output (parallel input/serial output mode). While shifting out the N parallel data bits on the serial output, the register shifts in N serial data bits from the serial input to be output on the parallel data outputs. During a parallel load operation, the N register bits are configured by the mode and control input to accept data from the parallel data inputs. Consequently, during a parallel load operation the first bit of the register is not available to load serial data (that will eventually be supplied to the Nth parallel output) from the serial input. Thus, serial operations cannot occur during parallel load operations and must be suspended.
It is therefore desirable to provide a method of serial and parallel data communication that overcomes the aforementioned limitation of the prior art.
The present invention provides a method of data conversion having an overlap in the operation of parallel and serial I/O (input/output) modes that improves upon the results obtained with the prior art previously described.